Integrated circuits (ICs) are manufactured using ever smaller feature sizes. One consequence of using smaller feature sizes is that wiring resources take on greater resistance and capacitance. The increased resistance and capacitance produce greater signal delays, which in turn may result in setup and hold timing violations in a circuit. The setup and hold violations prevent correct circuit operation and are often a limiting factor in increasing circuit performance.
The clock architecture of many ICs is relatively inflexible and may be unable to meet the stringent timing requirements of modern circuit designs. In many cases, the available clock architecture does not provide an adequate level of control over the clock signals propagated therein.